One application of a lithographic apparatus is to apply a desired pattern onto a target portion of a substrate. Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that circumstance, a patterning structure, such as a mask, may be used to generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies and/or portion(s) thereof) on a substrate (e.g. a wafer of silicon or other semiconductor material) that has a layer of radiation-sensitive material (e.g. a coating of resist). In general, a single substrate will contain a network of adjacent target portions that are successively irradiated via the projection system (e.g. one at a time).
Among current apparatus that employ patterning by a mask on a mask table, a distinction can be made between two different types of machine. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion at once; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. A projection beam in a scanning type of apparatus may have the form of a slit with a slit width in the scanning direction. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, which is incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a pattern (e.g. in a mask) is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (e.g. resist). Prior to this imaging procedure, the substrate may undergo various other procedures, such as priming, resist coating, and/or a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake, and/or measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device (e.g. an IC). Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all of which may be intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4.
The measurement and inspection procedure following development of the resist, referred to as “in-line” because it is carried out in the normal course of processing production wafers, serves two purposes. Firstly, it is desirable to detect any target areas where the pattern in the developed resist may be faulty. If a sufficient number of dies are faulty, the wafer can be stripped of the patterned resist and re-exposed, hopefully correctly, rather than making the fault permanent by carrying out a process procedure (e.g. an etch) with a faulty pattern. Secondly, the measurements may allow errors in the lithographic apparatus (e.g. in illumination settings or exposure times) to be detected and corrected for subsequent exposures.
However, some types of errors in the lithographic apparatus may not be easily detected or quantified from the patterns printed in exposures. Detection of a fault does not always lead directly to its cause. Thus, a variety of “off-line” procedures for detecting and measuring errors in the lithographic apparatus are known. These procedures may involve replacing the substrate with a measuring device or carrying out exposures of special test patterns, e.g. at a variety of different machine settings. Such off-line techniques take time, often a considerable amount, during which the apparatus cannot be used for production exposures. Therefore, in-line techniques (that is, ones which can be carried out using, or at the same time as, production exposures) for detecting and measuring errors in the lithographic apparatus may be preferred.
To measure dimensional errors, such as overlay and left-right dimensional differences caused by comatic aberration, image-based tools are used at present. Such tools include box-in-box (or frame-inframe) for overlay and scanning electron microscopes (SEM) to measure critical dimensions (CD) for coma. These techniques, as well as being off-line, have the disadvantage that they make localized measurements which do not necessarily accurately reflect the projection system or process behavior over the full die or target area.
One in-line method used in device manufacturing for measurements of linewidth, pitch and critical dimension (CD) makes use of a technique known as “scatterometry”. Methods of scatterometry are described in Raymond et al., “Multiparameter Grating Metrology Using Optical Scatterometry”, J. Vac. Sci. Tech. B, Vol. 15, no. 2, 361–368 (1997) and Niu et al., “Specular Spectroscopic Scatterometry in DUV Lithography”, SPIE, Vol. 3677 (1999). In some methods of scatterometry, white light is reflected by periodic structures in the developed resist, and the resulting reflection spectrum at a given angle is detected. The structure giving rise to the reflection spectrum is reconstructed, e.g. using Rigorous Coupled-Wave Analysis (RCWA) or by comparison to a library of spectra derived by simulation. However, the reconstruction of the structure is computationally very intensive, and the technique can suffer from low sensitivity and poor repeatability.
Other disclosures of the use of scatterometry in lithography include PCT Patent Publication No. WO 02/065545, which proposes to measure overlay by scatterometry measurements from two overlying gratings. This document suggests that if a sample of one of the gratings not overlain by the other is available, measurements may be taken to constrain the measurement of overlay derived from the two overlying gratings. U.S. Pat. No. 6,458,605 and U.S. patent application Ser. No. 2002/0041373 utilize reference libraries derived from measurements of reference structures to aid in derivation of information from scatterometry measurements. U.S. patent application Ser. No. 2002/0041373 also proposes printing a randomly distributed focus-energy matrix (FEM) of identical test gratings on a wafer and derives information from scatterometry measurements thereof, especially from differences between scatterometry measurements from different gratings in the matrix.